Senior R&D Engineer - RISC-V Memory Hierarchy (Italy/Europe based)

Company: Axelera AI
Location: Boston
Posted on: March 13, 2025

Job Description:

About Us is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.In just three years, we have raised a total of $120 million and have built a world-class team of 180+ employees (including 55+ PhDs with more than 40,000 citations), both remotely from 11 different countries and with offices in Belgium, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.We have also launched our Metis AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.Our unwavering commitment to innovation has firmly established us as a global industry pioneer.Are you up for the challenge?Position OverviewWe are seeking an experienced R&D Engineer with deep expertise in memory hierarchy design and validation for high-performance AI processing elements. The ideal candidate will have a strong background in designing, implementing, and validating advanced memory systems, including coherent cache architectures, as well as a thorough understanding of the RISC-V Weak Memory Model (RVWMO). This role is pivotal in shaping the memory subsystem of cutting-edge AI processing units.Key Responsibilities:

• Memory Hierarchy Design- Develop and optimize classical memory hierarchies (L1/L2/L3) tailored for AI processing elements, focusing on high performance and non-blocking designs.- Design and validate coherent cache architectures that meet the requirements of advanced AI workloads, ensuring scalability and efficiency.- Explore and implement innovative strategies to minimize latency and maximize throughput in memory-intensive applications.
• RISC-V Weak Memory Model (RVWMO)- Leverage a deep understanding of RVWMO to design memory systems that align with RISC-V specifications and constraints.- Model, analyze, and validate memory consistency across a variety of AI and general-purpose processing scenarios.- Contribute to the development of tools and methodologies for RVWMO validation and testing.
• Modelling and Validation- Develop and utilize simulation and hardware models to test and validate memory systems and coherence protocols.- Perform functional and performance validation to ensure reliability and efficiency of the designed memory hierarchies.- Collaborate with architecture and verification teams to align memory system behavior with processor and system-level requirements.
• Research and Innovation- Stay updated on the latest advancements in memory hierarchy design, RISC-V specifications, and AI processing architectures.- Propose and implement novel approaches to address emerging challenges in memory hierarchy design for AI workloads.- Contribute to technical publications, patents, and standards related to memory systems and AI hardware.Qualifications:
• Master's or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field with a focus on memory systems or AI processing.
• Experience in designing and optimizing L1/L2/L3 cache hierarchies for high-performance systems, particularly AI processing units.
• Strong understanding and practical experience with the RISC-V Weak Memory Model (RVWMO) in memory system design and validation.
• Hands-on experience with coherent cache architectures supporting scalable, efficient AI workloads.
• Proficiency in using simulation and hardware modeling tools for testing memory systems and validating performance.
• Passion for staying current with advancements in memory system design and AI technologies, with experience contributing to publications or patents.
• Strong ability to work with cross-functional teams and communicate complex technical ideas effectively.
• Proficiency in English, both spoken and written.LocationWe offer a flexible working arrangement, with options to:
• Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity.
• Work fully remotely from any European country (incl. the UK) you are already in.
• Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).Kindly note that priority will be given to candidates who are interested in being based in Italy.What We OfferThis is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.
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Keywords: Axelera AI, Boston , Senior R&D Engineer - RISC-V Memory Hierarchy (Italy/Europe based), Engineering , Boston, Massachusetts